1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a static random access memory in which ground lines for a plurality of memory cells are located in parallel to bit lines.
2. Description of Related Art
Referring to FIG. 5, there is shown an electric circuit diagram illustrating a static random access memory (SRAM) ordinarily used in the prior art. As shown in FIG. 5, the SRAM includes a plurality of memory cells 100, 101, . . . , 110, 111, . . . , which are located in the form of a matrix. A ground (GND) terminal of each memory cell is grounded. Bit lines D0, D0 bar, D1, D1 bar, . . . (in this specification, "bar" indicates that an upper bar is given to an associated Reference Sign) are connected to precharge transistors 10L, 10R, 11L, 11R, . . . , respectively. In addition, the bit lines D0, D0 bar, D1, D1 bar, are connected through column selectors 120L, 120R, 121L, 121R, . . . , respectively, to common bit lines CD and CD bar, which are connected to outputs of a write driver 130, respectively.
Now, a write operation in the prior art SRAM shown in FIG. 5 will be described. In an initial condition, the bit lines D0, D0bar, D1, D1 bar, . . . are precharged to a power supply potential Vdd through the precharge transistors 10L, 10R, 11L, 11R, . . . , respectively. For example, in an operation for writing "0" into the memory cell 100, firstly, the precharge transistors 10L, 10R, 11L, 11R, . . . are turned off, and corresponding column selectors 120L and 120R are turned on. With this arrangement, the outputs of the write driver 130 determined in accordance with the value of a write data D1 reach to the bit lines D0 and D0 bar through the common bit lines CD and CD bar. In this example, since DI=0, the potential of the bit line D0 is pulled down to a ground potential Vss, and the potential of the bit line D0 bar is maintained at the initial value of Vdd. Therefore, if the word line WL0 is brought to a high level by an associated driver 40, the value of the memory cell 100 is rewritten to "0". After the completion of the writing, the potential of the bit line D0 is returned to Vdd by action of the precharge transistor 10L.
Referring to FIG. 6, there is shown an electric circuit diagram of an SRAM disclosed by Japanese Patent Application Pre-examination Publication No. JP-A-09-231768, (an English abstract of JP-A-09-231768 is available and the content of the English abstract of JP-A-09-231768 is incorporated by reference in its entirety into this application). The SRAM shown in FIG. 6 is different from the SRAM shown in FIG. 5 in that a power supply terminal VD0 and a ground terminal VS0 of the memory cells 100, 101, . . . are connected to output terminals of a cell power supply voltage control circuit 70, respectively, and a power supply terminal VD1 and a ground terminal VS1 of the memory cells 110, 111, . . . are connected to output terminals of a cell power supply voltage control circuit 71, respectively. The cell power supply voltage control circuits 70, 71, . . . supply the power supply voltage Vdd and the ground potential Vss to the power supply terminals VD0, VD1, . . . and the ground terminals VS0, VS1, . . ., respectively, when power supply potential control signals PVC0, PVC1, . . . are a low level. To the contrary, when the power supply potential control signals PVC0, PVC1, . . . are a high level, the cell power supply voltage control circuits 70, 71, . . . supply the power supply terminals VD0, VD1, . . . with a second high potential side power supply potential Vdds which is lower than the power supply voltage Vdd by a predetermined level, and also supply the ground terminals VS0, VS1, . . . with a second low potential side power supply potential Vg2 which is higher than the ground potential Vss by a predetermined level. In a writing operation, only the power supply potential control signal corresponding to the selected memory cell is brought to the high level, so that the potential of the power supply terminal of the selected memory cell is lowered and the potential of the ground terminal of the selected memory cell is elevated. With this arrangement, the data holding capability of the selected memory cell is lowered, so that the writing operation executed by the write driver 130 is sped up.
In the prior art SRAM shown in FIG. 5, as mentioned above, after the completion of the writing, the potential of the bit line D0 is returned to Vdd by action of the precharge transistor 10L. However, the capacitance of the bit line is large, the power consumption is large, and therefore, the delay time is correspondingly large.
On the other hand, in the prior art SRAM shown in FIG. 6, since the bit line written with "0" is finally pulled down to the ground potential Vss, the power consumption cannot be reduced. Rather, since the cell power supply voltage control circuit 70 requires a new power for driving the power supply line VD0 and the ground line VS0 of the selected memory cell 100, the power consumption becomes larger than that of the SRAM shown in FIG. 5.
Generally, since the prior art SRAM includes a number of memory cells, the capacitance of the bit lines and the capacitance of the power supply line and the ground line of the memory cells are very large. Therefore, there is a problem that it is not so easy to reduce the delay time and the power consumption for driving the memory.